Since the first integrated circuit appeared, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components and semiconductor packages. For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, allowing more components to be integrated into a semiconductor chip or package. One approach for allowing more components to be integrated into a semiconductor structure is the adoption of three dimensional integrated circuit (3D IC) stacking techniques, in which silicon wafers and/or dies are stacked on one another. A technique for stacking semiconductor wafers and/or substrates in a semiconductor package employs the use of direct bonding between metal interconnection structures (e.g., direct copper to copper (Cu—Cu) bonding) of two substrates. However, to achieve successful bonding, precise alignment between two substrates and high co-planarity of interconnection structures on each substrate are involved to directly bond the interconnection structures of one substrate to the interconnection structures of another substrate. Moreover, warpage of the two substrates during the thermal cycle (due to, e.g., the relatively high temperature for direct bonding) may result in failure of bonding. Additionally, conventional Cu—Cu bonding is performed in an environment with high temperature, high pressure and/or a high degree of vacuum. Therefore, there is a need for, among other things, a semiconductor package that has a high tolerance for misalignment and a lack of co-planarity of interconnection structures during a bonding process.